14.22 CacheErr Register (27)

CacheErr Register Format for Secondary Cache Errors

Figure 14-26 shows the format of the CacheErr register when a secondary cache error occurs.



Figure 14-26 CacheErr Register Format for Secondary Cache Errors

EW: set when CacheErr register is already holding the values of a previous error

D: uncorrectable data array error (way1 || way0)

TA: uncorrectable tag array error (way1 || way0)

SIdx: secondary cache physical block index (PA[22:6] for 16-word block size or PA[22:7] for 32-word block size)

0: Reserved. Must be written as zeroes, and returns zeroes when read. (See page 224 of Errata.)

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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